The present invention relates to a memory device; and, more particularly, to a cell array of a nonvolatile ferroelectric memory device and an apparatus for driving such a cell array.
Generally, a nonvolatile ferroelectric memory device, i.e., a FeRAM (Ferroelectric Random Access Memory) device, processes signal data as fast as DRAM (Dynamic Random Access Memory) and it conserves stored data when power is not supplied so that this memory has been focused on the next generation storage device.
The cell structure of the FeRAM device is similar to that of the DRAM, i.e., the FeRAM device has one switching device (transistor) and one capacitor. Accordingly, the FeRAM device is a memory device having a unit cell of a 1T/1C structure and makes a use of a high remnant polarization of a ferroelectric material in a capacitor. This high remnant polarization contributes the FeRAM device to maintain stored data when an electric field is not applied to the capacitor.
FIG. 1 is a hysteresis loop illustrating characteristics of a nonvolatile ferroelectric memory device.
Referring to FIG. 1, the polarization induced by an electric field is not extinguished even though thereafter the electric field is not applied to the ferroelectric material and this feature is called xe2x80x9cremnant polarizationxe2x80x9d or xe2x80x9cspontaneous polarization.xe2x80x9d As shown in the hysteresis loop of FIG. 1, an amount of the polarization (d, a) is maintained when the applied voltage is xe2x80x9c0xe2x80x9d. The nonvolatile ferroelectric memory cell is indicative of a logic value xe2x80x9c1xe2x80x9d at the state of xe2x80x9cdxe2x80x9d and is indicative of a logic value xe2x80x9c0xe2x80x9d at the state of xe2x80x9ca.xe2x80x9d
A cell array of a nonvolatile ferroelectric memory device and a method for driving such a nonvolatile ferroelectric memory device will be described in detail referring to the accompanying drawings.
FIG. 2A is a schematic view of two unit cells in a conventional split word line structure, FIG. 2B is a circuit diagram for driving the unit cell in FIG. 2A and FIG. 3 is a timing chart illustrating the operation of the circuit in FIG. 2B.
First, referring to FIG. 2A, the unit cell of the split word line structure includes a first split word line SWL1 and a second split word line SWL2 which are extended in the direction of row, a first bit line BL1 and a second bit line BL2 crossing the first and second split word lines SWL1 and SWL2, a first transistor T1 having a gate connected to the first split word line SWL1 and a drain connected to the first bit line BL1, a first ferroelectric capacitor FC1 formed between the second split word line SWL2 and a source of the first transistor T1, a second transistor T2 having a gate connected to the second split word line SWL2 and a drain connected to the second bit line BL2, and a second ferroelectric capacitor FC2 formed between the first split word line SWL1 and a source of the first transistor T2.
A cell array is composed a plurality of unit cells mentioned above. In FIG. 2A, the unit cell makes up of a pair of split word lines SWL1 and SWL2, one bit line BL1, one transistor T1 and one ferroelectric capacitor FC1 in the meaning of data storage; however, the unit cell can be taken by a pair of split word lines SWL1 and SWL2, two bit lines BL1 and BL2, two transistors T1 and T2 and two ferroelectric capacitors FC1 and FC2 in the meaning of structure
The operation of the unit cell of the split word line structure will be describe below in detail referring to the FIG. 2B.
As shown in FIG. 2B, a plurality of split word line pairs, which has the first and second split word lines SWL1 and SWL2 respectively, are formed in a direction of row and a plurality of bit lines cross the split word pairs lines in a direction of column. As a result, in case where there are n cells (T1/1C) in a direction of row, n+1 bit lines are required to read out data from the unit cell. A sense amplifier for sensing a voltage difference between the first and second bit lines and amplifying the voltage difference are provided and two output nodes of the sense amplifier are respectively connected to a data bus line DL and a data bus bar line /DL.
At this time, a sensing enable signal SEN enables the sense amplifier to amplify the voltage difference and the amplified voltage difference signal from the sense amplifier is transmitted to the dada bus lines DL and /DL in response to a column selection signal CS which is applied to a switching transistor.
The operation of the nonvolatile ferroelectric memory device will be descried referring to FIG. 3 showing a timing chart of the circuit in FIG. 2B.
As illustrated in FIG. 3, at time t0, a chip enable signal /CE (in a low level at the time of activation) is activated to a low level when a bit line equalizing signal EQ is in a high level and the first and second split word lines SWL1 and SWL2 are in a low level. At this time, the bit lines SL1 and BL2 are precharged and the voltage level of the precharge generally set up to a threshold voltage of an NMOS transistor.
At time t1, the bit line equalizing signal EQ is in a low level for data sensing operation and the first and second split word lines SWL1 and SWL2 are activated to a high level. Data stored in the ferroelectric capacitor are transferred to the bit lines BL1 and BL2 according to the activation of the first and second split word lines SWL1 and SWL2. When logic data xe2x80x9c1 (high level voltage)xe2x80x9d is sorted in the ferroelectric capacitor, a voltage level on the bit line BL1 is highly increased because the point xe2x80x9cdxe2x80x9d is moved to the point xe2x80x9cfxe2x80x9d in FIG. 1 with the charge sharing between the bit line BL1 and the ferroelectric capacitor. However, when logic data xe2x80x9c0 (low level voltage)xe2x80x9d is sorted in the ferroelectric capacitor, a voltage level on the bit line BL1 is increased a little because the point xe2x80x9caxe2x80x9d is moved to the point xe2x80x9cfxe2x80x9d in FIG. 1 with the charge sharing between the bit line BL1 and the ferroelectric capacitor
At time t2, the sense amplifier is enabled in response to the sense amplifier enable signal SEN after the cell data are transferred to the bit lines BL1 and BL2 and the first and second split word lines SWL1 and SWL2 are activated.
On the other hand, since the logic data xe2x80x9c1xe2x80x9d can not be restored at a state that the first and second split word lines SWL1 and SWL2 are in a high level, data restoration should be achieved at time t3. At time t3, the column selection signal CS is activated to a high voltage level and the bit lines are electrically connected to the data bus lines. Data on the bit lines are transferred to the data bus lines at a read operation and data on the data bus lines are transferred to the bit lines are a write operation. Also, at time t3, the first split word line SWL1 is transited to a low level but the second split word line SWL2 keeps the voltage level low, thereby turning on the second transistor T2. At this time, in case where the second bit line BL2 is in a high level, a voltage level corresponding to the high level on the bit line BL2 is transferred to one of terminals of the second ferroelectric capacitor FC2. The other the other of terminals of the second ferroelectric capacitor FC2 is electrically connected to the first split word line SWL1 with a low level. Accordingly, the logic data xe2x80x9c1xe2x80x9d is restored.
At time t4, in case where logic data xe2x80x9c0xe2x80x9d are on the first bit line BL1 or the second bit line BL2, i.e., logic data xe2x80x9c0xe2x80x9d write operation, the first split word line SWL1 is transited to a high level and then the logic data xe2x80x9c0xe2x80x9d is written in the first ferroelectric capacitor FC1. However, in case where the first and second bit lines BL1 and BL3 are in a high level, there is no change of cell data.
Also, at time t5, the first split word line SWL1 is in a high level but the second split word line SWL2 transited to a low level, thereby turning on the first transistor T1. At this time, in case where the first bit line BL1 is in a high level, a voltage level corresponding to the high level on the bit line BL2 is transferred to one of terminals of the first ferroelectric capacitor FC1. The other the other of terminals of the first ferroelectric capacitor FC1 is electrically connected to the second split word line SWL2 with a low level. Accordingly, the logic data xe2x80x9c1xe2x80x9d is restored.
Finally, at time t6, the equalizing signal is activated to a high level so that charge sharing is achieved between the first and second bit lines BL1 and BL2 for the next operation.
As mentioned above, the conventional ferroelectric memory device has a split word line structure to decrease a load on a plate line; however, this has limitations on a chip size, especially in a cell array and a driving circuit of cells.
An object of the present invention is to provide a cell array of a nonvolatile ferroelectric memory device with a small chip size in a split word line structure, which is capable of dramatically decreasing a load on a plate line.
Another object of the present invention is to provide an apparatus for driving a cell array of a nonvolatile ferroelectric memory device with a small chip size in a split word line structure.
Further another object of the present invention is to provide a driving apparatus for improving a self-boost efficiency in a split word line driver for a cell array of a nonvolatile ferroelectric memory device with a low operation voltage.
According to an aspect of the present invention, there is provided a nonvolatile ferroelectric memory device comprising: a cell array region having first and second cell array blocks which are adjacent to each other and independently operate; a first drive region being adjacent to the first cell array block in the cell array region in order to drive first split words line which operate as plate lines of the first cell array block and word lines of the second cell array block; and a second drive region being adjacent to the second cell array block in the cell array region in order to drive first split word lines which operate as plate lines of the second cell array block and word lines of the first cell array block, wherein each of the first and second drive regions includes a plurality of split word line drivers and wherein each of the split word line drivers is connected to the plate lines of the first and second cell array blocks correspondent thereto.
According to another aspect of the present invention, there is provided a nonvolatile ferroelectric memory device comprising: a first cell array region having first and second cell array blocks which are adjacent to each other and independently operate; a first cell array region having third and fourth cell array blocks which are adjacent to each other and independently operate; a first drive region being adjacent to the first cell array block in order to drive first split word lines which operate as plate lines of the first cell array block and word lines of the second cell array block; a second drive region being adjacent to the second and third cell array blocks between the first and second cell array region in order to drive second split word lines which operate as plate lines of the second and third cell array blocks and word lines of the first and fourth cell array blocks; and a third drive region being adjacent to the fourth cell array block in order to drive third split word lines which operate as plate lines of the fourth cell array block and word lines of the third cell array block, wherein each of the first to fourth dive regions includes a plurality of split word line drivers and wherein each of the split word line drivers is connected to the plate lines of the first to fourth cell array blocks correspondent thereto.
According to still another aspect of the present invention, there is provided a nonvolatile ferroelectric memory device comprising: first and second cell array blocks which are adjacent to each other and independently operate; first split word lines operating as word lines of first memory cells corresponding to a first row of the first cell array block and as plate lines of second memory cells corresponding to a second row of the second cell array block; second split word lines operating as plate lines of the first memory cells and as word lines of third memory cells corresponding to a first row of the second cell array block; third split word lines operating as word lines of fourth memory cells corresponding to a second row of the first cell array block and as plate lines of the third memory cells; fourth split word lines operating as plate lines of the fourth memory cells and as word lines of the second memory cells; a first split word line driver for driving the second split word lines, being adjacent to the first cell array block and being connected to the plate lines of the first memory cells; a second split word line driver for driving the fourth split word lines, being adjacent to the first cell array block and being connected to the plate lines of the fourth memory cells; a third split word line driver for driving the third split word lines, being adjacent to the second cell array block and being connected to the plate lines of the third memory cells; and a fourth split word line driver for driving the first split word lines, being adjacent to the second cell array block and being connected to the plate lines of the second memory cells.
According to still another aspect of the present invention, there is provided a nonvolatile ferroelectric memory device comprising: first and second cell array blocks which are adjacent to each other and independently operate; third and fourth cell array blocks which are adjacent to each other and independently operate; first split word lines operating as word lines of first memory cells corresponding to a first row of the first cell array block, as plate lines of second memory cells corresponding to a second row of the second cell array block, as plate lines of third memory cells corresponding to a second row of the third cell array block and as word lines of fourth memory cells corresponding to a first row of the fourth cell array block; second split word lines operating as plate lines of the first memory cells and as word lines of fifth memory cells corresponding to a first row of the second cell array block; third split word lines operating as word lines of sixth memory cells corresponding to a second row of the first cell array block, as plate lines of the fifth memory cells, as plate lines of seventh memory cells corresponding to a first row of the third cell array block and as word lines of eighth memory cells corresponding to a second row of the fourth cell array block; fourth split word lines operating as plate lines of the sixth memory cells and as word lines of the second memory cells; fifth split word lines operating as plate lines of the fourth memory cells and as word lines of the seventh memory cells; sixth split word lines operating as plate lines of the eighth memory cells and as word lines of the third memory cells; a first split word line driver for driving the second split word lines, being adjacent to the first cell array block and being connected to the plate lines of the first memory cells; a second split word line driver for driving the fourth split word lines, being adjacent to the first cell array block and being connected to the plate lines of the sixth memory cells; a third split word line driver for driving the third split word lines, being adjacent to the second and third cell array blocks and being connected to the plate lines of the fifth and seventh memory cells; a fourth split word line driver for driving the first split word lines, being adjacent to the second and third cell array blocks and being connected to the plate lines of the third memory cells; a fifth split word line driver for driving the fifth split word lines, being adjacent to the fourth cell array block and being connected to the plate lines of the fourth memory cells; and a sixth split word line driver for driving the sixth split word lines, being adjacent to the fourth cell array block and being connected to the plate lines of the eighth memory cells.
According to still another aspect of the present invention, there is provided a nonvolatile ferroelectric memory device comprising: first and second cell array blocks which independently operate; an address path changing adjustor for decoding a plurality of row address predecoder input signals, outputting a plurality of row address predecoder output signals which are respectively corresponding to a plurality of split word lines, wherein the address path changing adjustor changes an input order of the row address predecoder input signals in response to a control signal to determine whether the first or second cell array block operates and produces order-changed row address predecoder output signals; a word line/plate line control signal path changing adjustor for receiving the row address predecoder output signals from the address path changing adjustor, word line control signal and a plate line control signal and outputting a plurality of split word lines driving signals, wherein the word line/plate line control signal path changing adjustor changes operational features of the split word lines driving signals in response to the control signal so that each of split word lines driving signals drive word lines or a plate line in the first and second cell array blocks; a level shifter boosting the plurality of the split word lines driving signals; and a plurality of split word lines driving part for driving the split word lines in response to output signals from the level shifter.
According to still another aspect of the present invention, there is provided a nonvolatile ferroelectric memory device comprising: first and second cell array blocks which independently operate in a split word line structure, wherein each of the first to fourth cell array blocks has a hierarchical bit line structure having a plurality of local bit lines correspondent to each of columns and a global bit line which is selectively connected to one of the plurality of the local bit lines by a plurality of switching transistors; driving means for driving a split word line in the split word line structure, wherein the driving means includes: an output terminal connected to the split word line; decoding means for receiving a plurality of row address signals and activating the split word line; pull-down means for carrying out a pull-down operation at the output terminal when the split word line are nonactivated; pull-down control means for controlling the pull-down means in response to an output signal from the decoding means and an external control signal; pull-up means for supplying a pumping voltage to the output terminal; and pull-up control means for controlling the pull-up means by applying the output signal from the decoding means to the pull-up means in response to word line control signal.
According to still another aspect of the present invention, there is provided a nonvolatile ferroelectric memory device comprising: a cell array region having first and second cell array blocks which are adjacent to each other and independently operate; a first drive region being adjacent to the first cell array block in the cell array region in order to drive first split word lines which operate as plate lines of the first cell array block and word lines of the second cell array block; a second drive region being adjacent to the second cell array block in the cell array region in order to drive first split word lines which operate as plate lines of the second cell array block and word lines of the first cell array block; and a sub drive region disposed between the first and second cell array regions, wherein the sub drive region controls a signal flow between the plate lines of the first cell array block and the word lines of the second cell array block and controls a signal flow between the plate lines of the second array block and the word lines of the first cell array block, wherein each of the first and second drive regions includes a plurality of split word line drivers and wherein each of the split word line drivers is connected to the plate lines of the first and second cell array blocks correspondent thereto.
According to still another aspect of the present invention, there is provided a nonvolatile ferroelectric memory device comprising: a first cell array region having first and second cell array blocks which are adjacent to each other and independently operate; a first cell array region having third and fourth cell array blocks which are adjacent to each other and independently operate; a first drive region being adjacent to the first cell array block in order to drive first split word lines which operate as plate lines of the first cell array block and word lines of the second cell array block; a second drive region being adjacent to the second and third cell array blocks between the first and second cell array region in order to drive second split word lines which operate as plate lines of the second and third cell array blocks and word lines of the first and fourth cell array blocks; a third drive region being adjacent to the fourth cell array block in order to drive third split word lines which operate as plate lines of the fourth cell array block and word lines of the third cell array block; a first sub drive region disposed between the first and second cell array regions, wherein the sub drive region controls a signal flow between the plate lines of the first cell array block and the word lines of the second cell array block and controls a signal flow between the plate lines of the second array block and the word lines of the first cell array block; and a first sub drive region disposed between the third and fourth cell array regions, wherein the sub drive region controls a signal flow between the plate lines of the third cell array block and the word lines of the fourth cell array block and controls a signal flow between the plate lines of the fourth array block and the word lines of the third cell array block, wherein each of the first to fourth dive regions includes a plurality of split word line drivers and wherein each of the split word line drivers is connected to the plate lines of the first to fourth cell array blocks correspondent thereto.
According to still another aspect of the present invention, there is provided a nonvolatile ferroelectric memory device comprising: first and second cell array blocks which independently operate in a split word line structure, wherein each of the first to fourth cell array blocks has a hierarchical bit line structure having a plurality of local bit lines correspondent to each of columns and a global bit line which is selectively connected to one of the plurality of the local bit lines by a plurality of switching transistors; driving means for driving a split word line in the split word line structure, wherein the driving means includes: an output terminal connected to a plate line of the first cell array block; decoding means for receiving a plurality of row address signals and activating the plate line of the first cell array block; pull-down means for carrying out a pull-down operation at the output terminal when the plate line of the first cell array block are nonactivated; pull-down control means for controlling the pull-down means in response to an output signal from the decoding means and an external control signal; pull-up means for supplying a pumping voltage to the output terminal; and pull-up control means for controlling the pull-up means by applying the output signal from the decoding means to the pull-up means in response to word line control signal.
According to still another aspect of the present invention, there is provided a nonvolatile ferroelectric memory device comprising: first and second cell array blocks which independently operate in a split word line structure, wherein each of the first to fourth cell array blocks has a hierarchical bit line structure having a plurality of local bit lines correspondent to each of columns and a global bit line which is selectively connected to one of the plurality of the local bit lines by a plurality of switching transistors; a split word line formed by a connection between a plate line of the first cell array block and a word line of the second cell array block; a switching transistor selectively connecting the plate line and the word line; and a control transistor for controlling a gate of the switching transistor and floating the plate line during the cell operation.
According to still another aspect of the present invention, there is provided a nonvolatile ferroelectric memory device comprising: a global bit line; a plurality of local bit lines, each of which is connected to a unit cell in a memory block; a plurality of switching means for selectively connecting a global bit line to one of the plurality of local bit lines; a reference line connected to a reference cell; sensing means for reading out data by comparing a voltage difference between the a global bit line a reference line; pull-down means for reducing a voltage level on the global bit line in response to a voltage level on the local bit line.